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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Mode Register  
Mode Register  
The mode register defines the specific mode of operation, including burst length (BL),  
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register  
is programmed via the LOAD MODE REGISTER command and retains the stored infor-  
mation until it is programmed again or the device loses power.  
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify  
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and  
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and  
Mn + 2 should be set to zero to select the mode register.  
The mode registers must be loaded when all banks are idle, and the controller must wait  
tMRD before initiating the subsequent operation. Violating either of these requirements  
will result in unspecified operation.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 1999 Micron Technology, Inc. All rights reserved.