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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Commands  
WRITE  
The WRITE command is used to initiate a burst write access to an active row. The values  
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-  
umn location. The value on input A10 determines whether auto precharge is used. If au-  
to precharge is selected, the row being accessed is precharged at the end of the write  
burst; if auto precharge is not selected, the row remains open for subsequent accesses.  
Input data appearing on the DQ is written to the memory array, subject to the DQM in-  
put logic level appearing coincident with the data. If a given DQM signal is registered  
LOW, the corresponding data is written to memory; if the DQM signal is registered  
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that  
byte/column location.  
Figure 12: WRITE Command  
CLK  
CKE HIGH  
CS#  
RAS#  
CAS#  
WE#  
Column address  
EN AP  
Address  
1
A10  
DIS AP  
Bank address  
BA0, BA1  
Valid address  
1. EN AP = enable auto precharge, DIS AP = disable auto precharge.  
Don’t Care  
Note:  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 1999 Micron Technology, Inc. All rights reserved.  
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