64Mb: x32
SDRAM
WRITE – DQM OPERATION 1
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM 0-3
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
t
CMS CMH
t
t
t
t
AS
AH
2
A0-A9
ROW
COLUMN m
t
AS
AH
ENABLE AUTO PRECHARGE
ROW
A10
t
DISABLE AUTO PRECHARGE
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DIN m
D
IN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
2
2
CH
2.75
2.75
7
1
1
CL
2
1.5
1
1.5
1
2
t
CK (3)
CK (2)
CK (1)
5
1
t
t
10
10
DS
1.5
15
1.5
18
2
20
20
RCD
20
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
52
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