64Mb: x32
SDRAM
SINGLEWRITE
T0
T1
T2
T3
T4
T5
T6
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
DH
DS
D
IN m
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
1
CL
2
DS
1.5
1.5
42
60
18
18
12
2
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
120,000
42
70
20
20
14
120,000
ns
ns
ns
ns
ns
t
t
t
10
20
1
10
20
1
55
15
15
RCD
CKH
1
RP
t
t
t
CKS
1.5
1.5
2
WR
2 CK
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 10ns is required between <DIN m> and the PRECHARGE command, regardless of frequency, to meet tWR.
3. A8, A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
47
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