64Mb: x32
SDRAM
WRITE – WITH AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM 0-3
A0-A9
t
t
AS
AH
3
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BANK
BANK
BA0, BA1
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
D
IN
m
D
IN m + 1
D
IN m + 2
DIN m + 3
DQ
2
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
2
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
1.5
1
1.5
1
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1
CH
2.75
2.75
7
DS
1.5
1.5
42
2
CL
2
RAS
RC
38.7 120,000
120,000
42
70
20
20
120,000
ns
ns
ns
ns
ns
t
CK (3)
CK (2)
CK (1)
CKH
5
55
15
15
60
t
t
t
t
t
10
20
1
10
20
1
RCD
18
RP
18
t
t
1
1.5
1
WR
2 CK
1 CLK+
6
1 CLK+
7
CKS
2
2
CMH
1
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
49
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