64Mb: x32
SDRAM
WRITE–FULL-PAGEBURST
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
( (
) )
( (
) )
DQM 0-3
A0-A9
t
t
AH
AS
( (
) )
( (
) )
1
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
( (
) )
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN m - 1
DQ
( (
) )
t
RCD
Full-page burst does
256 locations within same row
not self-terminate. Can
use BURST TERMINATE
2, 3
command to stop.
Full page completed
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
t
AH
AS
1
1.5
2
1
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
ns
ns
ns
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
1
CL
2
1.5
1
2
2
t
CK (3)
CK (2)
CK (1)
5
1
1
t
t
10
20
10
DS
1.5
15
1.5
18
2
20
RCD
20
*CAS latency indicated in parentheses.
NOTE: 1. A8 and A9 = “Don’t Care.”
t
2. WR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
51
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