64Mb: x32
SDRAM
ALTERNATINGBANKWRITEACCESSES 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DH
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DS
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN
b
DIN b + 1
DIN b + 2
DIN b + 3
DQ
t
t
t
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
AH
AS
1
1.5
2
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DH
DS
1
1.5
38.7
55
1
1.5
42
ns
ns
t
t
t
1.5
2.5
2.5
6
2
CH
2.75
2.75
7
RAS
RC
120,000
42
70
20
20
14
120,000
ns
ns
ns
ns
ns
ns
CL
2
60
t
CK (3)
CK (2)
CK (1)
5
RCD
15
18
t
t
t
10
20
1
10
20
1
RP
15
18
t
RRD
WR
10
12
t
t
CKH
1
1.5
1
2 CK
1 CLK+
6
1 CLK+
7
t
CKS
2
2
t
CMH
CMS
1
1
t
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
50
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