512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
t
HIGH at the desired clock edge (meeting CKS). See Figure 28 on page 36.
Fig u re 26: Po w e r-Do w n
( (
) )
CLK
( (
) )
> t
CKS
t
CKS
CKE
( (
) )
( (
) )
COMMAND
NOP
NOP
ACTIVE
( (
) )
t
All banks idle
RCD
RAS
RC
Input buffers gated off
t
t
Enter power-down mode.
Exit power-down mode.
DON’T CARE
De e p Po w e r-Do w n
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
Fig u re 27: De e p Po w e r-Do w n Co m m a n d
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
A0–A12
BA0, BA1
DON’T CARE
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
35
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