1Gb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
Figure 5: 64 Meg x 16 Functional Block Diagram
ODT
Bank 7
Bank 6
CKE
CK
CK#
Bank 7
Bank 6
Control
logic
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 1
CS#
RAS#
CAS#
WE#
Bank 2
Bank 1
ODT control
sw1 sw2 sw3
Vdd Q
CK, CK#
DLL
Bank 0
COL0, COL1
16
Bank 0
13
row-
address
latch
Memory array
(8,192 x 256 x 64)
Refresh
counter
8,192
16
16
16
13
Mode
registers
sw1 sw2 sw3
Row-
address
MUX
16
64
and
decoder
Read
latch
DRVRS
R1
R1
R2
R2
R3
R3
MUX
DATA
16
DQ0–DQ15
13
Sense amplifier
16,384
4
DQS
generator
UDQS, UDQS#
LDQS, LDQS#
64
Input
registers
2
sw1 sw2 sw3
2
2
R1
R1
R2
R2
R3
R3
I/O gating
DM mask logic
2
2
UDQS, UDQS#
LDQS, LDQS#
A0–A12,
BA0–BA2
2
8
Address
register
Bank
WRITE
FIFO
and
16
2
2
control
logic
Mask
3
256
(x64)
2
2
RCVRS
64
drivers
16
16
16
16
16
16
16
16
sw1 sw2 sw3
Column
decoder
16
CK out
CK in
64
CK, CK#
R1
R1
R2
R2
R3
R3
Column-
address
counter/
latch
8
2
Data
10
UDM, LDM
4
COL0, COL1
Vss Q
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
14
© 2004 Micron Technology, Inc. All rights reserved.
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