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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Electrical Characteristics and AC Operating Conditions  
Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions  
Notes 1–8 apply to the entire table  
DDR3-1866  
DDR3-2133  
Parameter  
Symbol  
Min  
Clock Timing  
Max  
Min  
Max  
Unit Notes  
Clock period average:  
DLL disable mode  
TC = 0°C to 85°C  
tCK  
(DLL_DIS)  
8
8
7800  
3900  
8
8
7800  
3900  
ns  
ns  
9, 42  
42  
TC = >85°C to 95°C  
Clock period average: DLL enable mode  
High pulse width average  
tCK (AVG)  
tCH (AVG)  
tCL (AVG)  
tJITper  
tJITper,lck  
tCK (ABS)  
See Speed Bin Tables (page 74) for tCK range allowed ns  
10, 11  
12  
0.47  
0.47  
–60  
0.53  
0.53  
60  
0.47  
0.47  
–50  
0.53  
0.53  
50  
CK  
CK  
ps  
Low pulse width average  
12  
Clock period jitter  
DLL locked  
DLL locking  
13  
–50  
50  
–40  
40  
ps  
13  
Clock absolute period  
MIN = tCK (AVG) MIN +  
tJITper MIN; MAX =  
tCK (AVG) MAX +  
tJITper MAX ps  
Clock absolute high pulse width  
Clock absolute low pulse width  
tCH (ABS)  
tCL (ABS)  
0.43  
0.43  
0.43  
tCK  
(AVG)  
tCK  
14  
15  
0.43  
(AVG)  
Cycle-to-cycle jitter  
DLL locked  
DLL locking  
tJITcc  
tJITcc,lck  
120  
100  
120  
100  
ps  
ps  
16  
16  
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