欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT41J256M4的Datasheet PDF文件第89页浏览型号MT41J256M4的Datasheet PDF文件第90页浏览型号MT41J256M4的Datasheet PDF文件第91页浏览型号MT41J256M4的Datasheet PDF文件第92页浏览型号MT41J256M4的Datasheet PDF文件第94页浏览型号MT41J256M4的Datasheet PDF文件第95页浏览型号MT41J256M4的Datasheet PDF文件第96页浏览型号MT41J256M4的Datasheet PDF文件第97页  
Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)  
Notes 1–8 apply to the entire table  
DDR3-1866  
DDR3-2133  
Parameter  
Symbol  
Min  
Refresh Timing  
Max  
Min  
Max  
Unit Notes  
REFRESH-to-ACTIVATE or REFRESH  
command period  
tRFC – 1Gb  
tRFC – 2Gb  
tRFC – 4Gb  
tRFC – 8Gb  
MIN = 110; MAX = 70,200  
MIN = 160; MAX = 70,200  
MIN = 260; MAX = 70,200  
MIN = 350; MAX = 70,200  
64 (1X)  
ns  
ns  
ns  
ns  
Maximum refresh  
period  
TC 85°C  
TC > 85°C  
TC 85°C  
TC > 85°C  
ms  
ms  
μs  
36  
36  
36  
36  
32 (2X)  
Maximum average  
periodic refresh  
tREFI  
7.8 (64ms/8192)  
3.9 (32ms/8192)  
μs  
Self Refresh Timing  
Exit self refresh to commands not requiring a  
locked DLL  
tXS  
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a  
CK  
CK  
CK  
CK  
CK  
Exit self refresh to commands requiring a  
locked DLL  
tXSDLL  
tCKESR  
tCKSRE  
tCKSRX  
MIN = tDLLK (MIN);  
MAX = n/a  
28  
Minimum CKE low pulse width for self re-  
fresh entry to self refresh exit timing  
MIN = tCKE (MIN) + CK; MAX = n/a  
MIN = greater of 5CK or 10ns; MAX = n/a  
MIN = greater of 5CK or 10ns; MAX = n/a  
Valid clocks after self refresh entry or power-  
down entry  
Valid clocks before self refresh exit,  
power-down exit, or reset exit  
Power-Down Timing  
CKE MIN pulse width  
tCKE (MIN)  
tCPDED  
Greater of 3CK or 5ns  
CK  
CK  
Command pass disable delay  
MIN = 2;  
MAX = n/a  
Power-down entry to power-down exit tim-  
ing  
tPD  
tANPD  
PDE  
MIN = tCKE (MIN);  
MAX = 9 * tREFI  
CK  
CK  
CK  
CK  
Begin power-down period prior to CKE  
registered HIGH  
WL - 1CK  
Power-down entry period: ODT either  
synchronous or asynchronous  
Greater of tANPD or tRFC - REFRESH command to CKE LOW time  
tANPD + tXPDLL  
Power-down exit period: ODT either  
synchronous or asynchronous  
PDX  
 复制成功!