1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Characteristics and AC Operating Conditions
tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 23 (page 57). Designs that were created prior to JEDEC
tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maxi-
mum.
39. Half-clock output parameters must be derated by the actual tERR10per and tJITdty when
input clock jitter is present. This results in each parameter becoming larger. The parame-
ters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are
required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 24 (page 60). This output load is used for ODT timings (see Figure 31
(page 71)).
41. Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.
44. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
V
IH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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