1Gb: x4, x8, x16 DDR3 SDRAM
Output Characteristics and Operating Conditions
Figure 30: Differential Output Signal
MAX output
V
OH
V
OX(AC)max
X
X
X
V
X
OX(AC)min
V
OL
MIN output
Reference Output Load
Figure 31 represents the effective reference load of 25Ω used in defining the relevant de-
vice AC timing parameters (except ODT reference timing) as well as the output slew rate
measurements. It is not intended to be a precise representation of a particular system
environment or a depiction of the actual load presented by a production tester. System
designers should use IBIS or other simulation tools to correlate the timing reference
load to a system environment.
Figure 31: Reference Output Load for AC Timing and Output Slew Rate
V
DDQ/2
V
DUT
REF
RTT = 25ȍ
DQ
DQS
VTT = VDDQ/2
DQS#
Timing reference point
ZQ
RZQ = 240ȍ
VSS
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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