1Gb: x4, x8, x16 DDR3 SDRAM
Output Characteristics and Operating Conditions
Output Characteristics and Operating Conditions
The DRAM uses both single-ended and differential output drivers. The single-ended
output driver is summarized below, while the differential output driver is summarized
in Table 48 (page 0±).
Table 47: Single-Ended Output Driver Characteristics
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Output leakage current: DQ are disabled;
IOZ
–5
5
μA
1
0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
Output slew rate: Single-ended; For rising and falling edges,
SRQse
2.5
6
V/ns 1, 2, 3, 4
measure between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC)
REF + 0.1 × VDDQ
=
V
Single-ended DC high-level output voltage
Single-ended DC mid-point level output voltage
Single-ended DC low-level output voltage
Single-ended AC high-level output voltage
Single-ended AC low-level output voltage
Delta RON between pull-up and pull-down for DQ/DQS
Test load for AC timing and output slew rates
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
MMPUPD
0.8 × VDDQ
V
V
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 3, 6
1, 2, 3, 6
1, 7
0.5 × VDDQ
0.2 × VDDQ
V
VTT + 0.1 × VDDQ
VTT - 0.1 × VDDQ
V
V
–10
10
%
Output to VTT (VDDQ/2) via 25Ω resistor
3
1. RZQ of 240Ω 1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-
Notes:
er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD
VSSQ = VSS).
;
2. VTT = VDDQ/2.
3. See Figure 31 (page 71) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching in the opposite direction. For all other DQ signal switch-
ing combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
5. See Table 37 (page 64) for IV curve linearity. Do not use AC test load.
6. See Table 49 (page 72) for output slew rate.
7. See Table 37 (page 64) for additional information.
8. See Figure 29 (page 70) for an example of a single-ended output signal.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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