1Gb: x4, x8, x16 DDR3 SDRAM
Power-Down Mode
Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP)
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
NOP
Tb2
NOP
Tb3
Tb4
CK#
CK
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
t
CPDED
IS
CKE
Address
Valid
A10
1
t
PD
WL = AL + CWL
WR
DQS, DQS#
DQ BL8
DI
DI
n
DI
DI
DI
DI
DI
DI
n + 7
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6
DI
n
DI
DI
DI
DQ BC4
n + 1 n + 2 n + 3
t
WRAPDEN
Start internal
precharge
Power-down or
self refresh entry
2
Indicates break
in time scale
Transitioning Data
Don’t Care
1. tWR is programmed through MR0[11:9] and represents tWRmin (ns)/tCK rounded up to
the next integer tCK.
2. CKE can go LOW 2tCK earlier if BC4MRS.
Notes:
Figure 103: REFRESH to Power-Down Entry
T0
T1
T2
T3
Ta0
Ta1
Ta2
Tb0
CK#
CK
t
t
t
CK
CH
CL
NOP
Command
REFRESH
NOP
NOP
NOP
Valid
t
t
CPDED
CKE (MIN)
t
t
PD
IS
CKE
t
t
REFPDEN
XP (MIN)
t
1
RFC (MIN)
Indicates break
in time scale
Don’t Care
1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
188
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