1Gb: x4, x8, x16 DDR3 SDRAM
SELF REFRESH Operation
Figure 96: Self Refresh Entry/Exit Timing
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
CK#
CK
tCKSRX1
tIH
tCKSRE1
tIS
tIS
tCPDED
CKE
Valid
Valid
Valid
tCKESR (MIN)1
tIS
2
ODT
ODTL
NOP
2
RESET#
5
NOP
3
4
6
7
Command
Address
SRX (NOP)
SRE (REF)
NOP
Valid
Valid
Valid
Valid
tRP8
tXS6, 9
tXSDLL7, 9
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
Indicates break
in time scale
Don’t Care
1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after en-
tering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not
apply; however, tCKESR must be satisfied prior to exiting at SRX.
Notes:
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both
RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6. tXS is required before any commands not requiring a locked DLL.
7. tXSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged, tRP must be met, and no data bursts can be in
progress.
9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising
clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that
tISXR is satisfied at Tc1.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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