1Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
Figure 92: WRITE (BL8) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
CK#
CK
Command
Address
WRITE
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
t
WL = AL + CWL
WR
DQS, DQS#
DQ BL8
DI
n
DI
DI
DI
DI
DI
DI
DI
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Indicates break
in time scale
Transitioning Data
Don’t Care
1. DI n = data-in from column n.
Notes:
2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
CK#
CK
Command
Address
WRITE
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
tWR
WL = AL + CWL
DQS, DQS#
DQ BC4
DI
n
DI
DI
DI
n + 1 n + 2 n + 3
Indicates break
in time scale
Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
Notes:
2. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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