1Gb: x4, x8, x16 DDR3 SDRAM
Power-Down Mode
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down IDD specifications are not applicable
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 81). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 90 (page 185) through Figure 1±6 (page 19±).
Table 81: Command to Power-Down Entry Parameters
Last Command Prior to
CKE LOW1
DRAM Status
Idle or active
Idle or active
Active
Parameter (Min)
tACTPDEN
tPRPDEN
Parameter Value
1tCK
Figure
ACTIVATE
PRECHARGE
Figure 104 (page 189)
Figure 105 (page 189)
Figure 100 (page 187)
Figure 101 (page 187)
1tCK
READ or READAP
tRDPDEN
tWRPDEN
RL + 4tCK + 1tCK
WL + 4tCK + tWR/tCK
Active
WRITE: BL8OTF, BL8MRS,
BC4OTF
Active
Active
WRITE: BC4MRS
WL + 2tCK + tWR/tCK
WL + 4tCK + WR + 1tCK
Figure 101 (page 187)
Figure 102 (page 188)
WRITEAP: BL8OTF, BL8MRS,
BC4OTF
tWRAPDEN
Active
Idle
WRITEAP: BC4MRS
REFRESH
WL + 2tCK + WR + 1tCK
1tCK
Greater of 10tCK or 24ns
tMOD
Figure 102 (page 188)
Figure 103 (page 188)
Figure 107 (page 190)
Figure 106 (page 190)
tREFPDEN
tXPDLL
tMRSPDEN
Power-down
Idle
REFRESH
MODE REGISTER SET
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous tANPD prior to CKE going LOW and remains asynchronous until tANPD +
tXPDLL after CKE goes HIGH.
Note:
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until tCPDED has been satis-
fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 2±6) for detailed ODT usage requirements in slow
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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