1Gb: x4, x8, x16 DDR3 SDRAM
Power-Down Mode
exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 82 (page 184).
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for power-
down duration is tPD (MAX) (9 × tREFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until tCKE has been
satisfied. A valid, executable command may be applied after power-down exit latency,
tXP, and tXPDLL have been satisfied. A summary of the power-down modes is listed be-
low.
For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-
to-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addi-
tion to meeting tPD when the REFRESH command is used between power-down exit
and power-down entry, two other conditions must be met. First, tXP must be satisfied
before issuing the REFRESH command. Second, tXPDLL must be satisfied before the
next power-down may be entered. An example is shown in Figure 1±0 (page 19±).
Table 82: Power-Down Modes
Power-
DRAM State
MR0[12]
DLL State
Down Exit
Relevant Parameters
tXP to any other valid command
tXP to any other valid command
tXPDLL to commands that require the DLL to be
locked (READ, RDAP, or ODT on);
tXP to any other valid command
Active (any bank open) “Don’t Care”
On
On
Off
Fast
Fast
Precharged
(all banks precharged)
1
0
Slow
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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