1Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command. The starting column and bank ad-
dresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is pre-
charged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Fig-
ure 85 (page 102) through Figure 93 (page 100), auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR± and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 85 (page 102). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
±tDQSS. Figure 86 (page 103) through Figure 93 (page 100) show the nominal case
where tDQSS = ±ns; however, Figure 85 (page 102) includes tDQSS (MIN) and tDQSS
(MAX) cases.
Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-
ly. If DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
t
provide a continuous flow of input data. The new WRITE command can be CCD clocks
following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 86 (page 103) and Figure 80
(page 103) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 88 (page 104).
t
Data for any WRITE burst may be followed by a subsequent READ command after WTR
has been met (see Figure 89 (page 104), Figure 9± (page 105), and Figure 91
(page 106)).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing tWR has been met, as shown in Figure 92 (page 100) and Figure 93
(page 100).
Both tWTR and tWR starting time may vary, depending on the mode register settings
(fixed BC4, BL8 versus OTF).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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