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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Figure 88: Nonconsecutive WRITE to WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
T17  
CK#  
CK  
Command  
WRITE  
Valid  
NOP  
NOP  
NOP  
NOP  
WRITE  
Valid  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Address  
WL = CWL + AL = 7  
WL = CWL + AL = 7  
DQS, DQS#  
DI  
n
DI  
DI  
DI  
DI  
DI  
DI  
DI  
DI  
b
DI  
DI  
DI  
DI  
DI  
DI  
DI  
DQ  
n + 1  
n + 2  
n + 3 n + 4  
n + 5  
n + 6  
n + 7  
b + 1  
b + 2  
b + 3  
b + 4 b + 5  
b + 6  
b + 7  
DM  
Transitioning Data  
Don't Care  
1. DI n (or b) = data-in for column n (or column b).  
Notes:  
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.  
3. Each WRITE command may be to any bank.  
4. Shown for WL = 7 (CWL = 7, AL = 0).  
Figure 89: WRITE (BL8) to READ (BL8)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
Ta0  
CK#  
CK  
Command1  
Address3  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
READ  
t
2
WTR  
Valid  
Valid  
t
t
WPRE  
WPST  
DQS, DQS#  
DQ4  
DI  
n
DI  
DI  
DI  
DI  
DI  
DI  
DI  
n + 7  
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
WL = 5  
Indicates break  
in time scale  
Transitioning Data  
Don’t Care  
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.  
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last  
write data shown at T9.  
Notes:  
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command  
at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.  
4. DI n = data-in for column n.  
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).  
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