1Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
Figure 80: Method for Calculating tLZ and tHZ
V
V
- xmV
V
+ 2xmV
OH
TT
V
+ xmV
- 2xmV
TT
OH
t
t
t
t
LZDQS, LZDQ
HZDQS, HZDQ
V
- xmV
V
V
+ 2xmV
+ xmV
TT
OL
T1
T2
V
- 2xmV
TT
OL
T1
T2
t
t
t
t
LZDQS, LZDQ begin point = 2 × T1 - T2
HZDQS, HZDQ end point = 2 × T1 - T2
1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK
(MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK
(MAX).
Notes:
2. The DQS HIGH pulse width is defined by tQSH, and the DQS LOW pulse width is defined
by tQSL. Likewise, tLZDQS (MIN) and tHZDQS (MIN) are not tied to tDQSCK (MIN) (early
strobe case), and tLZDQS (MAX) and tHZDQS (MAX) are not tied to tDQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The mini-
mum pulse width of the READ postamble is defined by tRPST (MIN).
Figure 81: tRPRE Timing
CK
V
TT
CK#
t
t
A
B
DQS
V
V
TT
TT
Single-ended signal provided
as background information
t
t
C
D
DQS#
Single-ended signal provided
as background information
T1
t
RPRE begins
t
RPRE
DQS - DQS#
0V
T2
Resulting differential
signal relevant for
RPRE specification
t
RPRE ends
t
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
168
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