1Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
tHZ and tLZ transitions occur in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Fig-
ure 8± (page 168) shows a method of calculating the point when the device is no longer
driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signal
at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQ
are defined as single-ended.
Figure 79: Data Strobe Timing – READs
RL measured
to this point
T0
T1
T2
T3
T4
T5
T6
CK
CK#
tDQSCK (MIN)
tDQSCK (MIN)
tDQSCK (MIN)
tDQSCK (MIN)
tHZDQS (MIN)
tLZDQS (MIN)
tQSH
tQSL
tQSH
tQSL
DQS, DQS#
early strobe
tRPST
tRPRE
Bit 0
Bit 1
Bit 2
Bit 3
tDQSCK (MAX)
Bit 4
Bit 5
Bit 6
Bit 7
tDQSCK (MAX)
tHZDQS (MAX)
tRPST
tLZDQS (MAX)
tDQSCK (MAX)
tDQSCK (MAX)
DQS, DQS#
late strobe
tRPRE
tQSH
Bit 0
tQSL
tQSH
tQSL
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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167
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