1Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
Figure 85: WRITE Burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
WL = AL + CWL
Bank,
Col n
2
Address
tDQSS t
tDSH
tDSH tWPST
tWPRE
DSH
tDSH
tDQSS (MIN)
DQS, DQS#
tDQSL
tDQSH
tDQSH
tDQSL tDQSH
tDQSL tDQSH tDQSL tDQSH tDQSL
3
DI
n
DI
DI
n + 2
DI
DI
DI
DI
DI
DQ
n + 1
n + 3
n + 4
n + 5
n + 6
n + 7
tWPRE
tDSH
tDSH
tDSH
tDSH
tWPST
tDQSS (NOM)
DQS, DQS#
tDQSL
tDSS
tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH
tDSS tDSS tDSS tDSS
3
DI
n
DI
n + 1
DI
DI
DI
DI
DI
DI
n + 7
DQ
n + 2
n + 3
n + 4
n + 5
n + 6
tDQSS
tWPRE
tWPST
tDQSS (MAX)
DQS, DQS#
tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH
tDQSL
DSS
t
t
t
t
t
DSS
DSS
DSS
DSS
3
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
Notes:
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST ac-
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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