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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Figure 78: Data Output Timing – tDQSQ and Data Valid Window  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
CK#  
CK  
Command1  
Address2  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
RL = AL + CL  
Bank,  
Col n  
tDQSQ (MAX)  
tRPST  
tDQSQ (MAX)  
tLZDQ (MIN)  
tHZDQ (MAX)  
DQS, DQS#  
tRPRE  
tQH  
DO  
tQH  
DO  
DQ3 (last data valid)  
DO  
n + 1  
DO  
DO  
DO  
n + 5  
DO  
DO  
n + 7  
n + 2  
n + 3  
n + 4  
n + 6  
n
DQ3 (first data no longer valid)  
DO  
DO  
DO  
DO  
DO  
DO  
DO  
DO  
n
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
n + 7  
DO  
DO  
DO  
DO  
DO  
DO  
DO  
DO  
n + 7  
All DQ collectively  
n
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
Data valid  
Data valid  
Don’t Care  
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.  
Notes:  
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at  
T0.  
3. DO n = data-out from column n.  
4. BL8, RL = 5 (AL = 0, CL = 5).  
5. Output timings are referenced to VDDQ/2 and DLL on and locked.  
6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.  
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within  
a burst.  
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