512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Se ria l Pre se n ce -De t e ct
Se ria l Pre se n ce -De t e ct
Ta b le 17:
Se ria l Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
VDDSPD
VIH
1.7
3.6
V
V
Supply voltage
VDDSPD × 0.7
VDDSPD + 0.5
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
VIL
–0.6
–
VDDSPD × 0.3
V
VOL
ILI
0.4
3
V
0.10
0.05
1.6
0.4
2
µA
µA
µA
mA
mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current
ILO
3
ISB
4
ICC
1
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
R
ICC
3
W
Ta b le 18:
Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
No t e s
tAA
tBUF
tDH
0.2
1.3
200
–
0.9
–
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
kHz
ns
µs
µs
ms
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
–
tF
300
–
2
SDA and SCL fall time
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
0
Data-in hold time
0.6
0.6
–
–
Start condition hold time
Clock HIGH period
–
50
–
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
1.3
–
0.3
400
–
2
SDA and SCL rise time
fSCL
–
SCL clock frequency
tSU:DAT
tSU:STA
tSU:STO
tWRC
100
0.6
0.6
–
Data-in setup time
–
3
4
Start condition setup time
Stop condition setup time
WRITE cycle time
–
10
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
14
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