512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD Sp e cifica t io n s
I
Ta b le 12:
DDR2 IDD Sp e cifica t io n s a n d Co n d it io n s (Die Re visio n A) – 2GB
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the
1Gb (256 Meg x 4) component data sheet
Pa ra m e t e r/Co n d it io n
Sym b o l
-667
-53E
-40E
Un it s
t
t
IDD0
1,620
1,440
1,260
mA
Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : CK = CK (IDD),
tRC = RC (IDD), RAS = RAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
t
t
t
IDD1
1,800
1,710
1,440
mA
Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : IOUT = 0mA;
t
t
t
t
t
BL = 4, CL = CL (IDD), AL = 0; tCK = CK (IDD), RC = RC (IDD), RAS = RAS
t
t
MIN (IDD), RCD = RCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
IDD4W
t
Pre ch a rg e p o w e r-d o w n cu rre n t : All device banks idle; tCK = CK (IDD);
IDD2P
IDD2Q
IDD2N
IDD3P
126
990
126
738
810
126
630
720
mA
mA
mA
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Pre ch a rg e q u ie t st a n d b y cu rre n t : All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Pre ch a rg e st a n d b y cu rre n t : All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
1,080
720
180
540
180
990
450
180
810
mA
mA
mA
Act ive p o w e r-d o w n cu rre n t : All device banks open;
Fast PDN exit
tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Act ive st a n d b y cu rre n t : All device banks open; tCK = CK (IDD),
t
IDD3N
IDD4W
1,260
tRAS = RAS MAX (IDD), RP = RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
t
t
t
2,880
2,880
4,680
2,340
2,610
4,500
1,980
1,980
3,960
mA
mA
mA
Op e ra t in g b u rst w rit e cu rre n t : All device banks open; Continuous
t
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = CK (IDD),
tRAS = RAS MAX (IDD), RP = RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
t
t
t
IDD4R
IDD5
Op e ra t in g b u rst re a d cu rre n t : All device banks open; Continuous burst
t
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = CK (IDD),
tRAS = RAS MAX (IDD), RP = RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
t
t
t
Bu rst re fre sh cu rre n t : tCK = CK (IDD); REFRESH command at every
t
tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD6
IDD7
126
126
126
mA
mA
Se lf re fre sh cu rre n t : CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
5,400
5,220
4,680
Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : All device banks interleaving
t
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = RCD (IDD) - 1 x tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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