512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Re g ist e r a n d PLL Sp e cifica t io n s
Ta b le 15:
Pa ra m e t e r
PLL Sp e cifica t io n s
CU877 device or equivalent JESD82-8.01
Sym b o l
Pin s
Co n d it io n
Min
Ma x
Un it s
VIH
VIL
VIN
VIH
VIL
VIX
RESET#
RESET#
LVCMOS
LVCMOS
0.65 × VDD
–
V
V
V
V
DC high-level input voltage
DC low-level input voltage
Input voltage (limits)
–
–0.3
0.35 × VDD
VDDQ + 0.3
–
RESET#, CK, CK#
CK, CK#
Differential input
Differential input
Differential input
0.65 × VDD
–
DC high-level input voltage
DC low-level input voltage
CK, CK#
0.35 × VDD mV
CK, CK#
(VDDQ/2) - (VDDQ/2) +
V
Input differential-pair cross
voltage
0.15
0.15
VID(DC)
VID(AC)
II
CK, CK#
CK, CK#
RESET#
CK, CK#
Differential input
Differential input
VI = VDDQ or VSSQ
VI = VDDQ or VSSQ
0.3
VDDQ + 0.4
V
V
Input differential voltage
Input differential voltage
Input current
0.6
VDDQ + 0.4
–10
–250
100
10
250
–
µA
µA
µA
IODL
RESET# = VSSQ; VI = VIH(AC) or
VIL(DC)
Output disabled current
IDDLD
IDD
CK = CK# = LOW
–
–
500
300
µA
Static supply current
Dynamic supply
n/a
CK, CK# = 270 MHz, all
outputs open
mA
(not connected to PCB)
CIN
Each input
VI = VDDQ or VSSQ
2
3
pF
Input capacitance
Ta b le 16:
Pa ra m e t e r
PLL Clo ck Drive r Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
Sym b o l
Min
Ma x
Un it s
tL
tLSI
–
15
4
µs
V/ns
kHz
%
Stabilization time
1.0
30
Input clock slew rate
33
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth (–3dB from unity gain)
0.0
2.0
–0.50
–
MHz
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
13
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