512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Re g ist e r a n d PLL Sp e cifica t io n s
Re g ist e r a n d PLL Sp e cifica t io n s
Ta b le 14:
Re g ist e r Sp e cifica t io n s
SSTU32866 devices or equivalent JESD82-16
Pa ra m e t e r
Sym b o l
Pin s
Co n d it io n
Min
Ma x
Un it s
VIH(DC)
Address,
control,
SSTL_18
VREF(DC) +125
VDDQ + 250
V
DC high-level
input voltage
command
VIL(DC)
VIH(AC)
VIL(AC)
Address,
control,
command
SSTL_18
SSTL_18
SSTL_18
0
VREF(DC) - 125
VDD
V
V
V
DC low-level
input voltage
Address,
control,
command
VREF(DC) + 250
0
AC high-level
input voltage
Address,
control,
VREF(DC) - 250
AC low-level
input voltage
command
VOH
VOL
II
Parity output
Parity output
All pins
LVCMOS
LVCMOS
1.2
–
–
0.5
5
V
V
Output high voltage
Output low voltage
Input current
VI = VDDQ or VSSQ
RESET# = VSSQ (IO = 0)
–5
–
µA
µA
mA
IDD
IDD
All pins
100
40
Static standby
All pins
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
–
Static operating
IDDD
IDDD
n/a
n/a
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle
–
–
Varies by
manufacturer
µA
µA
Dynamic operating
(clock tree)
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle;
One data input switching at
tCK/2, 50% duty cycle
Varies by
manufacturer
Dynamic operating
(per each input)
CI
CI
All inputs
except RESET#
VI = VREF ±250mV;
VDDQ = 1.8V
2.5
–
3.5
pF
pF
Input capacitance
(per device, per pin)
RESET#
VI = VDDQ or VSSQ
Varies by
Input capacitance
manufacturer
(per device, per pin)
Notes: 1. Timing and switching specifications for the register listed above are critical for proper
operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the
parameters for the specific device used on the module. Detailed information for this regis-
ter is available in JEDEC standard JESD82.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
12
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