8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).
SPD ACKNOWLEDGE
Acknoꢀledge is a softꢀare convention used to
indicate successful data transfers. The transmitting
device, either master or slave, ꢀill release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver ꢀill pull the SDA line LOW to acknoꢀledge
that it received the eight bits of data (Figure 3).
The SPD device ꢀill alꢀays respond ꢀith an ac-
knoꢀledge after recognition of a start condition and
its slave address. If both the device and a ꢀrite opera-
tion have been selected, the SPD device ꢀill respond
ꢀith an acknoꢀledge after the receipt of each subse-
quent eight-bit ꢀord. In the read mode the SPD device
ꢀill transmit eight bits of data, release the SDA line and
monitor the line for an acknoꢀledge. If an acknoꢀl-
edge is detected and no stop condition is generated by
the master, the slave ꢀill continue to transmit data.
If an acknoꢀledge is not detected, the slave ꢀill termi-
nate further data transmissions and aꢀait the stop
condition to return to standby poꢀer mode.
SPD START CONDITION
All commands are preceded by the start condition,
ꢀhich is a HIGH-to-LOW transition of SDA ꢀhen SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and ꢀill not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, ꢀhich is a LOW-to-HIGH transition of SDA
ꢀhen SCL is HIGH. The stop condition is also used to
place the SPD device into standby poꢀer mode.
SCL
SCL
SDA
SDA
START
BIT
STOP
BIT
DATA STABLE
DATA
CHANGE
DATA STABLE
Fig u re 1
Da t a Va lid it y
Fig u re 2
De fin it io n o f St a rt a n d St o p
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Fig u re 3
Ackn o w le d g e Re sp o n se Fro m Re ce ive r
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
7
MICRON [ MICRON TECHNOLOGY ]
