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M25PX16SOVZM6TP 参数 Datasheet PDF下载

M25PX16SOVZM6TP图片预览
型号: M25PX16SOVZM6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1418 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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M25PX16  
Instructions  
Figure 14. Read Data Bytes at higher speed (FAST_READ) instruction sequence  
and data-out sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
C
Instruction  
24-bit address  
23 22 21  
3
2
1
0
DQ0  
DQ1  
High Impedance  
S
C
47  
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46  
Dummy byte  
7
6
5
4
3
2
0
1
DQ0  
DQ1  
DATA OUT 2  
DATA OUT 1  
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB  
MSB  
MSB  
AI13737  
1. Address bits A23 to A22 are Don’t care.  
6.8  
Dual Output Fast Read (DOFR)  
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at  
higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin  
DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one  
doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed  
(FAST_READ) instruction.  
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual  
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,  
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory  
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency f ,  
C
during the falling edge of Serial Clock (C).  
The instruction sequence is shown in Figure 15.  
The first byte addressed can be at any location. The address is automatically incremented  
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole  
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.  
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