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M25PX16SOVZM6TP 参数 Datasheet PDF下载

M25PX16SOVZM6TP图片预览
型号: M25PX16SOVZM6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1418 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Instructions  
M25PX16  
the Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write  
PP  
Protect (W/V ) signal allow the device to be put in the hardware protected mode (HPM).  
PP  
The Write Status Register (WRSR) instruction is not executed once the hardware protected  
mode (HPM) is entered.  
Figure 12. Write Status Register (WRSR) instruction sequence  
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
C
Instruction  
Status  
Register In  
7
6
5
4
3
2
0
1
DQ0  
DQ1  
High Impedance  
MSB  
AI13735  
Table 8.  
Protection modes  
Write Protection  
of the Status  
Register  
Memory content  
Protected area(1) Unprotected area(1)  
W/VPP  
signal  
SRWD  
Mode  
bit  
1
0
0
0
Status Register is  
Writable (if the  
WREN instruction  
has set the WEL  
bit)  
Protected against  
Page Program,  
Sector Erase and  
Bulk Erase  
Ready to accept  
Page Program and  
Sector Erase  
Software  
protected  
(SPM)  
The values in the  
SRWD, BP2, BP1  
and BP0 bits can be  
changed  
instructions  
1
0
1
Status Register is  
hardware write  
protected  
Protected against  
Page Program,  
Sector Erase and  
Bulk Erase  
Ready to accept  
Page Program and  
Sector Erase  
Hardware  
protected  
(HPM)  
1
The values in the  
SRWD, BP2, BP1  
and BP0 bits  
instructions  
cannot be changed  
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in  
Table 3.  
The protection features of the device are summarized in Table 8.  
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial  
delivery state), it is possible to write to the Status Register provided that the Write Enable  
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless  
of the whether Write Protect (W/V ) is driven High or Low.  
PP  
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