256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Table 44: AC Read Specifications (Continued)
Parameter
Symbol
Min
Max
Unit
Notes
CLK frequency
tCLK
Easy BGA
QUAD+
–
52
MHz
1, 3, 5, 6
TSOP
40
–
CLK period
tCLK
Easy BGA
QUAD+
19.2
ns
ns
1, 3, 5, 6
1, 3, 5, 6
TSOP
25
5
CLK HIGH/LOW time
tCH/CL
Easy BGA
QUAD+
–
TSOP
9
CLK fall/rise time
tFCLK/RCLK
0.3
3
ns
ns
1, 3, 5, 6
1, 6
Synchronous Specifications5
Address setup to CLK
ADV# LOW setup to CLK
CE# LOW setup to CLK
CLK to output valid
tAVCH/L
tVLCH/L
tELCH/L
9
9
9
–
–
–
–
tCHQV /
tCLQV
Easy BGA
QUAD+
17
ns
1, 6
TSOP
20
-
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
tCHQX
tCHAX
Easy BGA
3
10
–
ns
ns
ns
1, 6
1, 4, 6
1, 6
-
tCHTV
tCHTX
17
QUAD+
TSOP
tCHVL
20
–
CLK valid to ADV# setup
WAIT hold from CLK
3
3
ns
ns
1
Easy BGA
QUAD+
–
1, 6
TSOP
5
1. See AC Test Conditions for timing measurements and maximum allowable input slew
rate.
Notes:
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to
tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specifica-
tion is satisfied first.
5. Synchronous read mode is not supported with TTL level inputs.
6. Applies only to subsequent synchronous reads.
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p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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