256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Test Conditions and Capacitance
AC Test Conditions and Capacitance
Figure 27: AC Input/Output Reference Timing
VCCQ
Input V
/2
Test points
V
/2 output
CCQ
CCQ
0V
1. AC test inputs are driven at VCCQ for logic 1 and at 0V for logic 0. Input/output timing
begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) <5ns. Worst-case speed oc-
curs at VCC = VCC (MIN).
Note:
Figure 28: Transient Equivalent Load Circuit
Device under
test
Out
C
L
1. See the Test Configuration for Worst-Case Speed Conditions table for component values.
2. CL includes jig capacitance.
Notes:
Table 42: Test Configuration: Worst-Case Speed Condition
Test Configuration
CL (pF)
VCCQ(MIN) standard test
30
Figure 29: Clock Input AC Waveform
tCLK
VIH
CLK
VIL
tCH/CL
tFCLK/RCLK
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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