256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 34: Continuous Burst Read with Output Delay
tAVCH
tVLCH tCHAX
tCHQV
tCHQV
tCHQV
CLK
tAVQV
tAVVH
tVHVL
A
tVHAX
ADV#
tELCH
tELVH
tELQV
CE#
OE#
tGLTX
tCHTV
tCHQV
tCHTX
tCHQX
WAIT
DQ
tGLQV
tGLQX
tCHQX
tCHQX
tCHQX
1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be
configured to assert either during or one data cycle before valid data.
Notes:
2. At the end of a wordline; the delay incurred when a burst access crosses a 16-word
boundary and the starting address is not 4-word boundary aligned.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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