256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 33: Synchronous Single-Word Array or Nonarray Read
tAVCH
tCHAX
tAVQV
CLK
A
tAVVH
tVHVL
tELCH
tVHAX
tVLVH
ADV#
tELVH
tEHQZ
tELQV
CE#
OE#
tGHQZ
tGLQX
tGLTX
tCHTV
tCHQV
tGHTZ
tCHTX
WAIT
tGLQV
tCHQX
DQ
1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be
configured to assert either during or one data cycle before valid data.
Notes:
2. In this example, an n-word burst is initiated to the flash memory array and is terminated
by CE# deassertion after the first word in the burst.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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