256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 30: Asynchronous Single-Word Read (ADV# LOW)
tAVAV
tAVQV
A
ADV#
CE#
tELQV
tEHQZ
tGHQZ
tGLQV
OE#
tGLTV
tGHTZ
WAIT
tGLQX
tELQX
DQ
tPHQV
RST#
1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted
LOW).
Note:
Figure 31: Asynchronous Single-Word Read (ADV# Latch)
tAVAV
tAVQV
A[MAX:5]
A[4:1]
tAVVH
tVHAX
tVHVL
ADV#
CE#
tELQV
tEHQZ
tGLQV
tGHQZ
OE#
tGHTZ
tGLTV
WAIT
tGLQX
tOH
tELQX
DQ
1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted
LOW).
Note:
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
86
© 2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
