256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
10. Add 10 ns if the write operation results in a RCR or block lock status change, for the sub-
sequent read operation to reflect this change.
11. These specs are required only when the device is in a synchronous mode and clock is ac-
tive during address setup phase.
12. This specification must be complied with by customer’s writing timing. The result would
be unpredictable if any violation to this timing specification.
Figure 36: Write to Write Timing
Figure 37: Asynchronous Read to Write Timing
tAVAV
tAVQV
tAVWH
tWHAX
A
tEHQZ
tELQV
CE#
tGLQV
tGHQZ
OE#
tELWL
tWLWH
tWHEH
WE#
tGLTV
tGHTZ
tOH
WAIT
tGLQX
tELQX
tWHDX
tDVWH
DQ
Q
D
tPHQV
RST#
1. WAIT deasserted during asynchronous read and during write. WAIT High-Z during write
per OE# deasserted.
Note:
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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