256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
Figure 40: Write to Synchronous Read Timing
Latency count
VLCH
t
t
t
AVCH
AVQV
CLK
t
t
t
AVWH
WHAX
t
CHAX
A
t
VHAX
VLVH
ADV#
t
t
t
t
ELWL
WHEH
t
EHEL ELCH
CE#
WHAV
t
WHCH/L
t
t
WLWH
WHVH
WE#
OE#
t
GLQV
t
t
GLTV
t
CHTV
WAIT
t
t
CHQV
CHQX
t
t
t
DVWH
WHDX
ELQV
CHQV
DQ
D
Q
Q
t
PHWL
RST#
1. WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.
10=0, WAIT asserted low).
Note:
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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