256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 33: Synchronous Single Word Array or Nonarray Read
tAVCH
tCHAX
tAVQV
CLK
A
tAVVH
tVHVL
tELCH
tVHAX
tVLVH
ADV#
tELVH
tELQV
tEHQZ
tGHQZ
CE#
OE#
tGLQX
tCHTV
tCHQV
tGHTZ
tCHTX
WAIT
tGLQV
tCHQX
DQ
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can
be configured to assert either during or one data cycle before valid data.
Notes:
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memo-
ry array and it is terminated by CE# deassertion after the first word in the burst.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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