256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 34: Continuous Burst Read with Output Delay (ADV# LOW)
t
AVCH
t
t
t
t
t
VLCH CHAX
CHQV
CHQV
CHQV
CLK
t
AVQV
t
t
AVVH
A
t
VHAX
VHVL
ADV#
t
ELCH
t
ELVH
t
ELQV
CE#
OE#
t
t
t
GLTV
CHTV
CHTX
WAIT
DQ
t
CHQV
t
GLQV
t
t
t
t
CHQX
CHQX
t
CHQX
CHQX
GLQX
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can
be configured to assert either during or one data cycle before valid data.
Notes:
2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word
boundary and the starting address is not 4-word boundary aligned.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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