256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Table 45: AC Read Specifications (Continued)
Number Symbol Parameter
Min
-
Max
Unit
MHz
MHz
ns
Note
R200
R201
R202
R203
fCLK
CLK frequency
Easy BGA/QUAD+
TSOP
52
40
-
1, 3, 5
-
tCLK
CLK period
Easy BGA/QUAD+
TSOP
19.2
25
5
-
ns
tCH/CL
CLK high/low time
Easy BGA/QUAD+
TSOP
-
ns
9
tFCLK/RCLK CLK fall/rise time
0.3
3
ns
Synchronous Specifications(5)
R301
R302
R303
R304
tAVCH/L Address setup to CLK
-
9
9
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
1, 6
tVLCH/L
tELCH/L
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
-
-
-
tCHQV /
Easy BGA/QUAD+
17
20
-
tCLQV
TSOP
-
1, 6
1, 6
R305
R306
R307
tCHQX
tCHAX
tCHTV
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
-
3
10
-
-
-
1, 4, 6
1, 6
Easy BGA/QUAD+
17
20
-
TSOP
-
R311
R312
tCHVL
tCHTX
CLK Valid to ADV# Setup
WAIT Hold from CLK
-
3
3
5
ns
ns
1
Easy BGA/QUAD+
TSOP
-
1, 6
-
1. See on page for timing measurements and max allowable input slew rate.
Notes:
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to
tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specifica-
tion is satisfied first.
5. Synchronous read mode is not supported with TTL level inputs.
6. Applies only to subsequent synchronous reads.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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