256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Test Conditions
AC Test Conditions
Figure 27: AC Input/Output Reference Timing
VCCQ
Input V
/2
Test points
V
/2 output
CCQ
CCQ
0V
1. AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0". Input/output tim-
ing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case
Note:
speed occurs at VCC = VCCMin
.
Figure 28: Transient Equivalent Load Circuit
Device under
test
Out
C
L
1. See the Test Configuration Component Value For Worst Case Speed Conditions table for
component values.
Notes:
2. CL includes jig capacitance.
Table 43: Test Configuration: Worst Case Speed Condition
Test Configuration
CL (pF)
VCCQMin Standard Test
30
Figure 29: Clock Input AC Waveform
tCLK
VIH
VIL
CLK
tCH/CL
tFCLK/RCLK
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
80
© 2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
