P30-65nm SBC
3.0
Pinouts/Ballouts
Figure 5: 56-Lead TSOP Pinout (64-Mbit and 128-Mbit Densities)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WAIT
A17
1
2
3
4
5
6
7
8
A16
A15
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
NC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
RFU
RFU
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RST#
VPP
56-Lead TSOP Pinout
14 mm x 20 mm
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
VSS
Top View
CE#
A1
Notes:
1.
2.
3.
4.
5.
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
A22 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
No Internal Connection on Pin 13; it may be driven or floated. For legacy 130nm designs, this pin can be tied to Vcc.
One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
11
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
