TC7109/A
3.1.6
DIFFERENTIAL REFERENCE
3.2.3
RUN/HOLD INPUT
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Roll-
over voltage is the main source of Common mode
error, caused by the reference capacitor losing or gain-
ing charge, due to stray capacity on its nodes. With a
large Common mode voltage, the reference capacitor
can gain charge (increase voltage) when called upon to
de-integrate a positive signal and lose charge
(decrease voltage) when called upon to de-integrate a
negative input signal. This difference in reference for
(+) or (–) input voltages will cause a rollover error. This
error can be held to less than 0.5 count, worst-case, by
using a large reference capacitor in comparison to the
stray capacitance. To minimize rollover error from
these sources, keep the reference Common mode
voltage near or at analog common.
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual slope ADC, as shown in
with the output latches updated after zero crossing in
the De-integrate mode. An internal pull-up resistor is
provided to ensure a HIGH level with an open input.
The RUN/HOLD input may be used to shorten conver-
sion time. If RUN/HOLD goes LOW any time after zero
crossing in the De-integrate mode, the circuit will jump
to auto-zero and eliminate that portion of time normally
spent in de-integrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in de-integrate. It will stay
in auto-zero for the minimum time and wait in auto-zero
for a HIGH at the RUN/HOLD input. As shown in
ods after RUN/HOLD is changed to HIGH, and the
converter will begin the integrate phase of the next
conversion.
The RUN/HOLD input allows controlled conversion
interface. The converter may be held at Idle in auto-
zero with RUN/HOLD LOW. The conversion is started
when RUN/HOLD goes HIGH, and the new data is
valid when the Status output goes LOW (or is trans-
ferred to the UART; see “Handshake Mode”). RUN/
HOLD may now go LOW, terminating de-integrate and
ensuring a minimum auto-zero time before stopping to
wait for the next conversion. Conversion time can be
minimized by ensuring RUN/HOLD goes LOW during
de-integrate, after zero crossing, and goes HIGH after
the hold point is reached.
The required activity on the RUN/HOLD input can be
provided by connecting it to the buffered oscillator
output. In this mode, the input value measured
determines the conversion time.
3.2
Digital Section
The digital section is shown in Figure 3-2 and includes
the clock oscillator and scaling circuit, a 12-bit binary
counter with output latches and TTL compatible three-
state output drivers, UART handshake logic, polarity,
over range, and control logic. Logic levels are referred
to as LOW or HIGH.
Inputs driven from TTL gates should have 3kΩ to 5kΩ
pull-up resistors added for maximum noise immunity.
For minimum power consumption, all inputs should
swing from GND (LOW) to V+ (HIGH).
3.2.1
STATUS OUTPUT
During a conversion cycle, the Status output goes high
at the beginning of signal integrate and goes low one-
half clock period after new data from the conversion
has been stored in the output latches (see Figure 3-1).
The signal may be used as a “data valid” flag to drive
interrupts, or for monitoring the status of the converter.
(Data will not change while status is low.)
3.2.2
MODE INPUT
The Output mode of the converter is controlled by the
MODE input. The converter is in its “Direct” Output
mode, when the MODE input is LOW or left open. The
output data is directly accessible under the control of
the chip and byte enable inputs (this input is provided
with a pull-down resistor to ensure a LOW level when
the pin is left open). When the MODE input is pulsed
high, the converter enters the UART Handshake mode
and outputs the data in 2 bytes, then returns to “Direct”
mode. When the MODE input is kept HIGH, the
converter will output data in the Handshake mode at
the end of every conversion cycle. With MODE =
0
(direct bus transfer), the send input should be tied to
V+. (See “Handshake Mode”.)
©
2006 Microchip Technology Inc.
DS21456C-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
