TC7109/A
ZI
Integrator
Saturates
AZ
Zero Integrator
Phase forces
Integrator Output
to 0V
Integrator Output
for Over Range Input
No Zero Crossing
Zero Crossing
Occurs
Zero Crossing
Detected
Integrator Output
for Normal Input
AZ
Phase I
INT
Phase II
DE
Phase III
AZ
Internal Clock
Internal Latch
Status Output
2048
Counts
Min.
Fixed
2048
Counts
4096
Counts
Max
Number of Counts to Zero Crossing
Proportional to V
IN
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
FIGURE 3-1:
Conversion Timing (RUN/HOLD) Pin High
High Order
Byte Outputs
Low Order
Byte Outputs
B
B
B
12 11 10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
TEST
17
POL OR
3
4
5
6
7
8
9 10 11 12 13 14 15 16
18
19
20
LBEN
HBEN
14 Three-State Outputs
14 Latches
CE/LOAD
12-Bit Counter
Latch
Clock
COMP OUT
AZ
INT
DE ( )
ZI
To
Analog
Section
Conversion
Control Logic
Oscillator and
Clock Circuitry
Handshake
Logic
2
26
22 23 24 25
21
27
1
STATUS
RUN/ OSC OSC OSC BUFF MODE
IN OUT SEL OSC
OUT
SEND
GND
HOLD
FIGURE 3-2:
Digital Section
DS21456C-page 10
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
