PIC24FJ64GA104 FAMILY
PIC24FJ64GA104 family devices implement a total of
16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2
Data Address Space
The PIC24F core has a separate, 16-bit wide data mem-
ory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 4-3.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the program space visibility area (see
Section 4.3.3 “Reading Data from Program Memory
Using Program Space Visibility”).
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24FJ64GA104 FAMILY DEVICES
MSB
Address
LSB
Address
MSB
LSB
0000h
0001h
SFR
Space
SFR Space
Data RAM
07FFh
0801h
07FEh
0800h
Near
Data Space
1FFFh
2001h
1FFEh
2000h
Implemented
Data RAM
27FFh
2801h
27FEh
2800h
Unimplemented
Read as ‘0’
7FFFh
8001h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
FFFEh
Note:
Data memory areas are not shown to scale.
2010 Microchip Technology Inc.
DS39951C-page 33
MICROCHIP [ MICROCHIP ]
