PIC24FJ64GA104 FAMILY
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
PC
Working Register Array
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
Table Memory Page Address Register
Program Space Visibility Page Address Register
Repeat Loop Counter Register
CPU Control Register
TBLPAG
PSVPAG
RCOUNT
CORCON
FIGURE 3-2:
PROGRAMMER’S MODEL
15
0
W0 (WREG)
Divider Working Registers
Multiplier Registers
W1
W2
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
W15
Frame Pointer
Stack Pointer
0
Stack Pointer Limit
Value Register
0
SPLIM
22
0
0
PC
Program Counter
7
0
0
0
Table Memory Page
Address Register
TBLPAG
7
Program Space Visibility
Page Address Register
PSVPAG
15
15
Repeat Loop Counter
Register
RCOUNT
IPL
SRH
SRL
0
— — — — — — —
ALU STATUS Register (SR)
DC
RA N OV Z
C
2 1 0
15
0
— — — — — — — — — — — — IPL3 PSV — —
CPU Control Register (CORCON)
Registers or bits shaded for PUSH.Sand POP.Sinstructions.
2010 Microchip Technology Inc.
DS39951C-page 27
MICROCHIP [ MICROCHIP ]
