PIC18F2480/2580/4480/4580
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f,
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits TO and
PD are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Q Cycle Activity:
Q1
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2009 Microchip Technology Inc.
DS39637D-page 383
MICROCHIP [ MICROCHIP ]
