PIC18F2480/2580/4480/4580
25.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F2480/2580/4480/4580 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEPor CLRWDTinstruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
25.2.1
CONTROL REGISTER
Register 25-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
.
FIGURE 25-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
Wake-up
from Power
÷128
INTRC Source
Managed Modes
Change on IRCF bits
CLRWDT
WDT
Reset
Reset
Programmable Postscaler
1:1 to 1:32,768
All Device Resets
WDT
4
WDTPS<3:0>
Sleep
DS39637D-page 358
© 2009 Microchip Technology Inc.
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